Active matrix array lining-base and mfg. method thereof


Application Number: 00104942
Application Date: 2000.03.30
Publication Number: 1269522
Publication Date: 2000.10.11
Priority Information: 1999/4/2 JP 096854/1999
International: G02F1/1345;G02F1/136
Applicant(s) Name: Matsushita Electric Industries Co., Ltd.
Address:
Inventor(s) Name: Hidese Kiji;Tsuboi Nobuyuki;Okita Akitaka
Patent Agency Code: 31100
Patent Agent: li jialin
Abstract An active matrix array substrate having active elements aligned in matrix, and more than one scanning line and data line for driving the active elements. Each scanning line is connected to a common scanning bus through a scanning line test resistance, and each data line is connected to a common data bus through a data line test resistance. Each data line is configured with a metal multilayer, and each scanning line test resistance and data line test resistance are configured with a lowest metal layer of this metal multilayer. With this configuration, electrostatic breakdown between a scanning line 4 and data line 5 or neighboring data lines 5 during the manufacturing process is preventable. Accordingly, an active matrix array substrate and its manufacturing method which delivers good yields are achieved.