Adder and its implementation method


Application Number: 00104959
Application Date: 2000.04.05
Publication Number: 1316693
Publication Date: 2001.10.10
Priority Information:
International: G06F7/42
Applicant(s) Name: Duosi Science and Technology Industry Region Co Ltd, Beijing
Address:
Inventor(s) Name: Wang Gongben;Xia Hong;Liu Dali
Patent Agency Code: 11038
Patent Agent: fan benguo
Abstract A WLX adder is disclosed, which uses the halving principle for grouping. In order to improve the parallelism of sum calculation and carry calculatino, the sum predication for each small adder unit and the in-advance carry technique for the carry of each small adder unit are utilized. A reverse logic method is used for circuit design.