Bidirectional bus circuit capable of avoiding floating state and proceeding bidirectional data transmission


Application Number  00128733 Application Date  2000.09.18
Publication Number  1303056 Publication Date  2001.07.11
Priority Information   2000/1/5 JP 387/00  
International
Classification
 G06F13/40  
Applicant(s) Name  Mitsubishi Electric Corp.  
Address    
Inventor(s) Name  Makino Hiroyuki  
Patent Agency Code  72001 Patent Agent  liu zongjie
AbstractA data bus included in a bi-directional bus circuitry is divided into a first bus node Nb1 and a second bus node Nb2 by a repeater circuit (50). The repeater circuit includes a first tristate buffer 51 for amplifying and transmitting data from the first bus node Nb1 to the second bus node Nb2, and a second tristate buffer connected in reverse direction 52. When the data bus is not used, the first and second tristate buffers are both activated, and the repeater circuit functions as a latch circuit. Therefore, when the data bus is not used, the potential level of the data bus can be prevented from being left unfixed, ensuring stable operation.