Circuits and method for making bus reset reliably and irrelevant to length of cable


Application Number: 00109441
Application Date: 2000.06.23
Publication Number: 1279429
Publication Date: 2001.01.10
Priority Information: 1999/6/23 JP 176169/1999
International: G06F13/42
Applicant(s) Name: NEC Corp.
Address:
Inventor(s) Name: Tanjo Takayuji
Patent Agency Code: 11021
Patent Agent: zhu haibei
Abstract In a bus reset process of an IEEE-1394 transceiver circuit, a signal is transmitted to a serial bus and a signal from the bus is received and applied to a higher layer. When a transmit bus reset signal is detected in the transmitted signal, a masking signal is exclusively applied to the higher layer in response to the start timing of the transmit bus reset signal. A receive bus reset signal is detected in the received signal. A count operation is started for incrementing a count value in response to the start timing of the detected receive bus reset signal until the count value exceeds a predetermined value. The received signal is then exclusively applied to the higher layer in response to the end timing of the count operation.