Clock signal control method and circuit and data transterring device using them


Application Number: 00109431
Application Date: 2000.06.23
Publication Number: 1279550
Publication Date: 2001.01.10
Priority Information: 1999/6/24 JP 178382/1999
International: H03K5/00;H04L7/02
Applicant(s) Name: NEC Corp.
Address:
Inventor(s) Name: Saiki Takanori
Patent Agency Code: 11219
Patent Agent: mu dejun
Abstract A control circuit for clock signals which enables phase errors of respective clock signals to be averaged out as the phase difference between clock signals is kept. Multi-phase clock signals are interacted to average out respective phase error components between respective phases. To this end, plural stages of the averaging circuits for averaging out errors of respective phases are provided and clock signals are passed through the averaging circuits to effect averaging progressively to average out the phase errors for the entire clock signals.