CMOS semiconductor integral circuit

Application Number: 00107261
Application Date: 2000.04.30
Publication Number: 1273437
Publication Date: 2000.11.15
Priority Information: 1999/5/6 JP 125781/1999; 1999/9/9 JP 255248/1999
International: H01L21/82;H01L27/092
Applicant(s) Name: Matsushita Electric Industrial Co., Ltd.
Address:
Inventor(s) Name: Ikoma Heiji;Inagi Zentsugu;Koishi Hirohyuki
Patent Agency Code: 11021
Patent Agent: wang huimin
Abstract In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor)with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.