Correction for metal inlaid wiring form


Application Number: 00108534
Application Date: 2000.05.12
Publication Number: 1274171
Publication Date: 2000.11.22
Priority Information: 1999/5/14 US 09/313564
International: H01L21/302;H01L21/314;H01L21/768
Applicant(s) Name: IBM Corp.
Address:
Inventor(s) Name: S. G. Bangbatill;E. J. White
Patent Agency Code: 72001
Patent Agent: liang yong
Abstract A method and structure for planarizing a semiconductor surface having topographical irregularities including coating the semiconductor surface with a polish stop layer, depositing a filling layer over the polish stop layer, the filling layer having a thickness greater than the depth of the topographical irregularities and selectively polishing the filling layer down to the stop layer.