Digital phase-locked loop circuit


Application Number: 00107617
Application Date: 2000.05.15
Publication Number: 1278675
Publication Date: 2001.01.03
Priority Information: 1999/6/18 KR 22986/99
International: H03L7/08
Applicant(s) Name: LG Information Communication Co., Ltd.
Address:
Inventor(s) Name: Lee Young-Dai;Son Soo-Hyun
Patent Agency Code: 11219
Patent Agent: yu mang
Abstract A digital processing PLL circuit includes a phase difference computing unit for comparing a first clock signal inputted from.a reference clock generator and a second clock signal fedback from a VCO and computing a phase difference value during a calculation time unit; a control unit for controlling a manner that a phase difference correcting value corresponding to the phase difference value is read from a predetermined look-up table and the output clock signal of the VCO is synchronized with the first clock signal; and a memory unit for storing the look-up table. The value of the phase difference is computed with hardware by using an adder and a buffer. so it's provided to reduce the cost and execute rapid control.