Integrated circuit having frequency division operation testing function

Application Number: 00108972
Application Date: 2000.05.24
Publication Number: 1274850
Publication Date: 2000.11.29
Priority Information: 1999/5/25 JP 145111/1999
International: G01R31/28
Applicant(s) Name: Seiko Clock Corp.
Inventor(s) Name: Nakamura Hideyuki
Patent Agency Code: 11038
Patent Agent: yang guoxu
Abstract When a reset terminal 6 is separate off from the exterior input source to input a clock pulse to a clock input terminal 1, the first frequency dividing circuit 2 changes the a first frequency of the clock pulse to lower frequency and transmittes the pulse signal to the reset terminal 6 via a signal control circuit 5.An operation of the first frequency dividing circuit 2 is confirmed from the pulse signal of the reset terminal 6. When a second dividing circuit 3 is tested, the clock pulse input to the clock input terminal 1 is stopped after an 'H' signal is supplied once to the reset terminal 6.