Logic circuit


Application Number: 00108351
Application Date: 2000.02.29
Publication Number: 1301023
Publication Date: 2001.06.27
Priority Information: 1999/12/22 JP 365664/99
International: G11C7/00;G11C11/34
Applicant(s) Name: Sony Corp.
Address:
Inventor(s) Name: Hirairi Koji
Patent Agency Code: 72001
Patent Agent: fu kang
Abstract The logic circuit includes a logic circuit portion comprised of a dual-rail type logic tree, a synchronization type sensing latch means comprised of a sense amplifier for differentially amplifying results of evaluation of the logic circuit portion in synchronization with a clock, a logic tree disconnection controlling circuit, and a group of switches for disconnection of the logic tree, and a set and reset latch means for holding a logic for one cycle of the synchronization signal. In an idle stage, the sense amplifier is deactivated, the dual-rail type logic tree unit and sensing latch are connected, and the output terminals of the dual-rail type logic tree are short-circuited. In the drive stage, the sense amplifier is activated and the output terminals of the dual-rail logic tree are opened. In the final determination stage, the sense amplifier is activated and the logic tree and sensing latch unit are disconnected.