Method and apparatus for producing test model of circuit block capable of reducing load and time


Application Number: 00109030
Application Date: 2000.06.02
Publication Number: 1276534
Publication Date: 2000.12.13
Priority Information: 1999/6/2 JP 155764/1999
International: G01R31/317
Applicant(s) Name: NEC Corp.
Address:
Inventor(s) Name: Otsuka Shigekazu
Patent Agency Code: 11219
Patent Agent: mu dejun
Abstract In a method for generating a test pattern for testing at least one circuit block (24-1, 24-2, 24-3) of a semiconductor device including a control circuit (21) connected to the circuit block the above-mentioned test pattern is generated by converting a common test pattern (11) for the circuit block with reference to a data conversion library (12) corresponding to characteristics of the control circuit.