Multistage interference canceller using first level and second level path timing

Application Number: 00107233
Application Date: 2000.04.27
Publication Number: 1272009
Publication Date: 2000.11.01
Priority Information: 1999/4/27 JP 120520/1999
International: H04J13/02
Applicant(s) Name: NEC Corp.
Address:
Inventor(s) Name: Donburi Tatsuya
Patent Agency Code: 11021
Patent Agent: zhu jingui
Abstract Each of path search unit 41 . . . 4N performs a path-searching on a received signal rin to output a primary path timing signal 8 indicating primary path timings. Each of IEUs 11 . . . 1N in a first stage performs a despreading or the like on the basis of the primary path timing signal 8 to generate a symbol replica signal 51 and a chip replica signal 6. Subtractor 31 subtracts the sum of chip replica signals 6 from the received signal rin to generate a residual signal 7. Each of path search units 41 . . . 4N performs a path-searching on the residual signal 7, and outputs a secondary path signal 9 indicating secondary path timings. Each of IEUs 11 . . . 1N in the second and the following stages performs a despreading or the like on the basis of the secondary path timing signal 9.