Non-volatile semiconductor memroy device and control method for data erasion


Application Number: 00108883
Application Date: 2000.03.31
Publication Number: 1270394
Publication Date: 2000.10.18
Priority Information: 1999/4/2 JP 097003/1999; 1999/6/28 JP 182248/1999
International: G11C11/34;G11C16/14
Applicant(s) Name: Toshiba K. K.
Address:
Inventor(s) Name: Yamamura Toshio;Sigiura Yoshihisa;Kanasawa Kazuku
Patent Agency Code: 11038
Patent Agent: wang yonggang
Abstract A memory cell array is divided into left and right cell arrays 1L and 1R, each of which comprises a plurality of blocks. Data erase is sequentially controlled by an erase control circuit 8 on the basis of an erase command flag incorporated into a command register 4 and an address incorporated into an address register 5. Batch erase is carried out with respect to selected blocks of the right and left cell arrays 1L and 1R. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays 1L and 1R in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase.