Tag Archives: 0.05

Processaable isolation layer grid inlay technology used in sub 0.05 micrometer MOS device

Application Number  00129485 Application Date  2000.12.29 Publication Number  1319884 Publication Date  2001.10.31 Priority Information   2000/1/21 US 09/488806   International Classification  H01L21/336   Applicant(s) Name  International Business Machine Corp.   Address     Inventor(s) Name  D.C. Bode;H.I. Hanafei;W.C. Nazils   Patent Agency Code  72001 Patent Agent  chen ji AbstractTechniques to fabricate sub-0.05 mum MOSFET devices… Read More »