Time digit converter and locking circuit of using same, and its method


Application Number: 00108553
Application Date: 2000.05.15
Publication Number: 1274200
Publication Date: 2000.11.22
Priority Information: 1999/5/15 KR 17506/99; 1999/10/13 KR 44298/99
International: G11C7/00;H03L7/08
Applicant(s) Name: Samsung Electronics Co., Ltd.
Address:
Inventor(s) Name: Lee Gan-Yun;Chong Gi-Wook
Patent Agency Code: 11105
Patent Agent: ma ying
Abstract An integrated circuit having a locking circuit and method using the same are provided. The locking circuit includes a time-to-digital converter. The time-to-digital converter includes first and second delay chains, each for delaying one of two input signals at predetermined intervals. The time-to-digital converter also includes first and second phase comparators, each for comparing the delayed signal with the other signal and generating a digital signal. The locking circuit converts the phase difference between a feedback signal and an internal clock signal into a delay control signal group using the time-to-digital converter. The delay control signal group controls the delay time of a mirror delay circuit to rapidly minimize the phase difference between the feedback signal and the internal clock signal.